Jobs for People with MS: National MS Society

Job Description

In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel.

This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.

Join Our Team: Altera, IPSE group is responsible for High-Speed Protocol IP portfolio. As Lead DV Engineer focusing on IP Verification and Validation, you will be responsible for carrying out design validation for Intel next generation IP's across the Intel FPGA IP product portfolios. The charter of IP verification and validation team is to verify and validate the IP for robust functionality from functional simulation and FPGA development kit based HW validation. The verification and validation areas encompass IP's for high-speed transceiver protocols.

Key Responsibilities:

· Create comprehensive verification and validation plan based on IP/FPGA architecture specifications and carry out all the IP validation tasks. The plan encompasses functional, system level and hardware verification and validation perspectives.

· Developing IP/subsystem/system level testbench, creating tests, and necessary coverage goals based on specification to verify the implementation. Writing directed and random test cases, debugging failures, filing and closing bugs.

· Reviewing verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics.

· Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits maximizing FPGA hardware capability to bring substantial improvement to IP quality and usability for Altera FPGA IP product portfolios.

· Integration of Synopsys VIP and their usage to aid end to end testing Ethernet/MACSEC/IPSEC protocol testing.

· Developing verification and validation tools and flows, as needed.

· Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market.

· Excellent communication skills.

Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

· BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study plus 8 years of industry experience.

· 8+ years of experience developing verification collateral in Verilog, System Verilog, and UVM.

· 7 years with Ethernet protocol verification is required.

· Fluency in UVM, must have 7 years prior work experience with complex coverage driven random constraint UVM environments.

· Should have expertise in network security protocols: Ethernet/MACSEC/IPSEC end to end testing. Prefer candidates to be well versed in PCIe and Memory security solutions.

· 7 years of experience creating test plan from High level Specification and developing test cases.

· 7 years of experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.

· 4+ years of leading complex projects and leadership experience working with cross functional teams.

Preferred Qualifications:

· Must have put together complex UVM environments from scratch.

· FPGA experience is a plus.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.