Jobs for People with MS: National MS Society

Job Description

As a DFT Engineer, you will play a pivotal role in our semiconductor design team, focusing on the physical implementation of advanced ASIC designs. You will work closely with architecture, RTL, Logic design, Verification and Test & Validation teams to ensure high-performance, ASIC designs are successfully implemented and delivered to production. The Sr. DFT engineers primarily role is to plan and scope DFT structures based on product test specifications, implement scan, generate test patterns, and collaborate with ATE test engineer. DFT engineer utilizes industry standard EDA vendor tool, flow, and methodologies for DFT implementation, test constraints and signoff. This team consists of a director, manager, and 15 engineers that are made of up of mostly Physical Design engineers and 2 DFT Engineers. The DFT Engineers report to the director. This DFT Engineer will be responsible for the DFT process from RTL to Post-silicon. The current DFT engineer doesnt have enough bandwidth or experience to cover the entire spectrum of DFT responsibilities the team currently has. This team is a very experienced PD team and needs this person to fit within that team most of the engineers on this team have 20+ years of experience working together. It would be ideal to have depth in scan logic. They have older nodes and advanced nodes so someone having both experiences and a good breadth of process technologies is necessary. The chip size they have worked with doesnt matter for DFT, but more so DFT test structures and logic of the design need to be able to easily understand RTL coding, logic synthesis and able to coordinate verification and work with the test engineers.

Team culture easy going, ethical, hard working and can maintain work-life balance.

Benefits:

 Work-life balance: Flexible 9/80 Work schedules with every other Friday off

 Competitive benefit package: Including options for healthcare and medical coverage, 401K Retirement Benefits with company contribution, as well as a generous holidays and PTO allotment. Selected candidate may also be eligible for short-term and long-term incentives.

 Pay Range: $150,000-195,000 annually, with offers based on candidate experience

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to HR@insightglobal.com .

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Skills and Requirements

BS/MS in Electrical, Electronics, Computer Engineering, or 15 years of experience in related field or Ph.D. with 8 years of experience in related field

 Understanding of ASIC design principles, architectures, and semiconductor manufacturing processes.

 Must be able to scope DFT plan and strategy for all designs based on product DFT architecture specification requirements and compliance with test standards (JTAG) including DFT RTL coding.

 Hands-on DFT implementation which includes scan insertion and integration of specific test structure logic into RTL for BIST, MBIST, BSCAN), Scan verification

 Hands-on experience in developing and validating test constraints as per the DFT plan

 Experience in ATPG environment setup and generating patterns as per required coverage set for the test signoff and simulation environment for scan patterns.

 ATE bring up and post-silicon test debug as required (usually involves collaboration with ATE engineer and Validation team)

 Experience with Synopsys TestMax and/or Siemens Tessent tools for DFT implementation and closure

 Proficient in verilog, logic design and scripting-languages (tcl, python, csh/bash). Design Verification for clock/JTAG/DFT IP, Logic Design, Timing Analysis is a plus

 Experience with Physical Design null

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion,sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military oruniformed service member status, or any other status or characteristic protected by applicable laws, regulations, andordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to HR@insightglobal.com.